In an electronic device manufacturing process, a mask is formed on a processing target layer, and etching is performed to transfer a pattern of the mask to the processing target layer. As an example of such an etching, plasma etching may be used. The masks used for plasma etching are formed by the photolithographic technique. Therefore, a limit dimension of the pattern formed on the processing target layer depends on a resolution of the mask formed by the photolithographic technique. The resolution of the pattern of the mask has a resolution limit. There is a growing demand for high integration of an electronic device and it is required to form a pattern having a dimension smaller than the resolution limit. For this reason, as disclosed in, for example, U.S. Patent Application Publication No. 2016/0379824, a technique has been proposed in which the dimensional shape of the pattern is adjusted to reduce the width of an opening of the pattern.